A 25?102GHz 2.81?5.64mW tunable divide-by-4 in 28nm CMOS

A wideband tunable divide-by-4 is designed and realized in 28nm bulk CMOS. A systematic design methodology to maximize the locking range over power consumption ratio is proposed. The test chip core area is only 25.6×24.8μm² and measurements repeated over several samples demonstrate an operating frequency range from 25GHz to 102GHz with a maximum power consumption of 5.64mW from a 0.9V supply. The frequency band from 44.3GHz to 90GHz is covered in only three steps with a minimum fractional bandwidth in exceed of 20% and power consumption less than 4.7mW demonstrating the effectiveness of the proposed design techniques.