Area-efficient high-throughput sorted QR decomposition-based MIMO detector on FPGA

This paper aimed to improve MIMO detector´s performance in both throughput and cost. Thus, it presents a FPGA architecture implementation for the SQRD detection in a 4 × 4 16-QAM MIMO wireless communication systems. The exploitation of fine-grained parallelism and coarse-grained parallelism strategies are responsible for bettering the performance of the implementation. Besides, this paper proposes a method to ensure the correctness of the implementation of time-sharing modules, which is general and applicable to any MIMO detector implementation. The work results in a real-time FPGA-based implementation delivering 32 MSQRD/s with 5.2 us latency and lowering more than 50\% cost in hardware resources on a Xilinx Virtex6.