A low-cost and flexible FPGA implementation for SPECK block Cipher

Field Programmable Gate Arrays (FPGAs) are quickly becoming a fundamental flexible integrated circuit building block of choice for many applications such as aerospace, military and defense systems. In addition, instead of using a large number of logic gates, FPGA today can be used to implement any circuits that you want. Furthermore, FPGAs can be configured as system on a chip (SoC). In June 2013 American National Security Agency (NSA) proposed a new block cipher family named SPECK. In this paper, two methods are used to implement this algorithm. First method is used high level synthesis for give more flexibility and to achieve suitable throughput in our implementation. Second method is used bit serialized architecture to achieve minimum area and cost in our design. In second methodology, we have implemented SPECK, with a very small hardware architecture only costs 34 slices and 68 LUTs on a Spartan-3 FPGA. The results show that with a tantamount security level, SPECK is 85% smaller than AES, 68% smaller than PRESENT (a standardized low-cost AES Superseded and an ISO lightweight algorithm).