CMOS circuits for cell-level design of a racetrack memory

This paper deals with a so-called racetrack memory (also commonly known as a domain-wall memory). Novel circuits for implementing the write, the read and the shift operations of the racetrack cell are introduced; the proposed circuits are very efficient in terms of numerous figures of merit, such as delay, power dissipation, and power delay product (PDP). An extensive analysis of variation in the operation of a racetrack memory is also presented; this analysis shows that the racetrack memory offers significant advantages when non-volatile storage is required.