WiCkeD tool-based design method for divide-by-2 circuits with multiple loads

This work describes an optimization tool-based design method for a Current Mode Logic CML divide-by-2 circuit embedded in a frequency synthesizer for RFID-protocol based transceiver implementation. Designed for driving multiple loads with asymmetric input capacitance to be driven at system level (through the PLL output frequency generation), the circuit was optimized for operation at lowest power consumption in a strict locking range (output frequency: 2.4 GHz to 2.475 GHz). By applying CMOSXFAB 0.18 μm technology, the schematic level design with subsequent optimization stage was performed at Virtuoso Analog Design Environment through MunEDA WiCkeD.