Error-tolerant and energy-efficient FFT with dynamic current and frequency scaling (DCFS)

This work utilizes the dynamic current scaling (DCS) to control the pMOS array for outputting the sufficient operating current. It makes the FFT modules work under the lower power-consummation operating mode. Furthermore, to guarantee the DCS current is enough for the whole system. We need the online error detection. In this work, we just apply the adaptive sequential elements to determine the critical path delay and whether the timing constraint is met or not. When the error occurred, the system will perform the re-computing process to increase clock rate to recover errors via dynamic frequency scaling (DFS). All this work was synthesized and simulated with TSMC 65nm technology.