Towards tolerating soft errors in memory applications

These days´ memory elements in digital systems have become more prone to soft errors or transient errors due to integration in circuits, smaller size of transistors and capacitors, combining with cosmic ray effects and many more reasons. Soft errors in memory elements have been a greater concern than soft errors in logic circuits since memories are used to hold the largest numbers and bits susceptible to particle strikes. This paper introduces a high level error detection and correction method to provide more immunity to memory elements. This paper introduces an algorithm which can decide if there is a single bit error or double bit error. If a single bit is erroneous then it determines which portion (among information bits or check bits) of the code word contains the error and then performs operation to detect and correct the error. And in case of two erroneous bits, it performs the detection and correction operation for the whole code word. The proposed approach can correct up to 2 bit upsets in a 15 bit data block within lesser computation cycles compared to existing dominant approach.