Implimentation and evaluation of an efficient clock distribution network for deep-submicron technology

A differential clock distribution network using current mode logic (CML) buffer and RCL interconnect model for low-skew is presented in this paper. We investigate attenuation and skew of the proposed clock distribution network. An efficient differential CML buffer is used as it is capable of operating with low voltage and high frequency which makes this clock distribution network more advantageous over the conventional models. Different clock distribution networks with clock trees such as H-tree, X-tree and binary tree are designed. Those networks are analyzed by using different technological nodes, such as 22nm, 32nm, 45nm. Due to the high clock frequency, more accurate RCL interconnect model has been explored. According to the analysis, compared to other clock trees, X-tree has less skew of 179ps with large area and the binary tree has a constant delay ratio.