A modified structure for symmetrical and asymmetrical configuration of multilevel inverter

MLI is receiving tremendous popularity due to its reduced voltage stress across switches and low THD in output voltage. MLI incorporates large number of semiconductor switches which increases complexity and reduces efficiency. Therefore, a great deal of attention is paid towards reducing the number of semiconductor switches. The reduction of switch count reduces the size, cost and complexity and enhances overall performance. In this paper a modified topology for symmetrical and asymmetrical configuration of MLI is proposed for increased output voltage levels with reduced number of semiconductor switches. A comprehensive study of proposed configuration of MLI is carried out in terms of switch counts and blocking voltage. The detailed simulation study of the proposed concept has been carried out using MATLAB/SIMULINK and validated experimentally.