DocumentCode
3737773
Title
Improved phase-locked loop under heavily distorted grid condition
Author
Liran Zheng;Hua Geng;Geng Yang
Author_Institution
Department of Automation, Tsinghua University, Beijing, China, 100084
fYear
2015
Firstpage
4778
Lastpage
4783
Abstract
This paper proposes a novel phase-locked loop (PLL) for grid synchronization based on the moving average filter (MAF) and the weighted least squares estimation (WLSE) scheme, namely WLSE-PLL. The MAF can eliminate all the odd-order harmonics and the fundamental negative-sequence component. The WLSE is employed to estimate the fundamental positive-sequence component (FPS). Combining the zero crossing detection (ZCD) and the frequency locked-loop (FLL), the WLSE-PLL is also adaptive to frequency deviation. Through analysis and simulation, the WLSE-PLL is proved to have a fast response and a satisfactory performance even under heavily distorted grid conditions including three-phase unbalance, dc offset and harmonics.
Keywords
"Phase locked loops","Power harmonic filters","Frequency estimation","Harmonic analysis","Synchronization","Frequency locked loops","Estimation"
Publisher
ieee
Conference_Titel
Industrial Electronics Society, IECON 2015 - 41st Annual Conference of the IEEE
Type
conf
DOI
10.1109/IECON.2015.7392847
Filename
7392847
Link To Document