Energy minimization in the time-space continuum

Can time-multiplexing save energy? Recent theoretical work suggests that time multiplexed architectures might use less energy than fully spatial FPGAs. Spatial FPGAs conserve energy by avoiding instruction fetch, exploiting locality, and exploiting low activity on wires. However, since they dedicate physical switches and wires to a single signal, they can be larger than designs that time multiplex these physical resources. Can the area savings from time multiplexing reduce wire lengths significantly enough to provide a net win against increased switching activity and the addition of instruction energy? Mapping designs from the VTR 7 no memory benchmarks and spatial FFTs, we show that spatial FPGAs remain the most energy efficient architecture at least up to half a million 4-LUTs. We explain why this is and explore how sensitive our results are to technology and usage assumptions.