Design of low power, high PSRR low drop-out voltage regulator

This paper presents a low power, low drop-out (LDO) voltage regulator, designed and implemented using 0.18 micron CMOS process. With a supply voltage of 1.8V, 50mA current and with a single compensation capacitor of 1pF. A constant transconductance current reference is used as a bias circuit for the Error Amplifier. The maximum output load current is 50mA at a regulated output voltage of 1.68V.The voltage regulator delivers a full load transient response of 5.5mV overshoot and 3.4mV undershoot. Furthermore, the LDO PSRR rating is -73dB @ 16.7MHz, and a relatively low power of 90mW.