Analog realization of a low-voltage two-order selectable fractional-order differentiator in a 0.35um CMOS technology

The analog realization of a selectable fractional-order differentiator (FOD) in a microelectronics scale is mainly the focus of this study. From this design, the order of differentiation can be selected between FOD(0.25) and FOD(0.50). While the aim is to make the hardware implementation as compact and small as possible, the authors employed reusability of resistors and capacitors when switching from one order to the other. The top-level schematic was generated using S-Edit while the physical layout implementation was outlined using L-Edit. The resulting integrated circuit (IC) design has a total chip area of 4.05mm × 3.10mm or equivalent to a final area of 12.56mm². The whole chip is powered using dual supply voltage of only +0.75V Vdd and -0.75V Vss. Each order of differentiation was characterized in its magnitude and phase response in the working bandwidth from 10Hz to 1kHz.