5 GS/s Track and Hold circuit in 90-nm CMOS technology process

A CMOS Track-and-Hold circuit which can accommodate 700 MHz to 1 GHz of input frequency with a sampling rate of 5 GS/s is presented. This T/H circuit acts as a sampling circuit in front end of high speed analog-to-digital converters that are applicable in television and radio signal transmissions. The T/H circuit, which includes transmission gate switches, hold capacitors and output buffers, is designed and simulated in SAED 90-nm CMOS process technology using Synopsys Galaxy Custom Designer Tool with 1.2 V supply voltage. An open-loop T/H architecture paired with fully differential structure is designed to withstand high frequency input signal and to minimize harmonic distortions. The T/H circuit occupies an active chip core area of 0.00195 mm2.