Resource-saving compile flow for coarse-grained reconfigurable architectures

Coarse-Grained Reconfigurable Architectures (CGRA) are promising accelerators with high performance and power-efficiency. Most compilers map loop kernels of the compute-intensive applications onto CGRA through modified modulo scheduling algorithms. EPIMap converts the problem into finding a subgraph of time extend CGRA that matches modified data flow graph (DFG). Therefore, the number of nodes and edges in the final modified DFG decides the resources used in time extend CGRA, thus influence the performance. To this end, it is essential to find an effective way reducing nodes and edges in the modified DFG to save the resources in time extend CGRA. Besides, existing compilers lack a systematic way to modify DFG. To address these problems, this paper firstly choose to use a new CGRA with global synchronization mechanism, which help reducing the nodes and edges in modified DFG. Secondly, proposing a complete and systematic DFG modification flow which saves more resources. Finally, to reduce the compile time, a resource-monitoring mapping heuristic with lower time complexity is provided. The experiment result shows that our global synchronized CGRA can save at most 17% computing and routing resources compared with general CGRA, our DFG modifying flow can save at most 20% computing and routing resources compared with EPIMap. Besides, our resource-saving compile flow generate performance as good as EPIMap while taking less compile time.