Cross-Chip: Low power processor-to-memory nanophotonic interconnect architecture

As processors continue towards many-cores, on-chip memory interconnects are anticipated to consume a substantial portion of overall chip power and area. In this paper, we propose Cross-Chip (XChip), a new core-to-memory network-on-chip architecture that significantly improves system power efficiency with minimal network area footprint and high performance communication for future many-core processors. This is achieved by relocating the global shared last-level cache off chip, closer to main memory, and by bridging the processor-to-memory gap with high bandwidth, low power nanophotonics. By implementing the network across separate chips with optical fibers, free-space can be leveraged to avoid additional insertion losses from waveguide intersections. Our simulation and analytical results show that when our proposed interconnect architecture is compared to several other photonic architectures, XChip can reduce total network area by 11%, and reduce laser power consumption by 49% with only small penalties to overall system IPC.