SOAP - Sea of atomic processors

This paper proposes a massively parallel computer architecture appropriate for implementation in late and post silicon technologies. These technologies promise to integrate more than a billion components on a chip or other substrates, but of which some may fail temporarily or permanently. In the proposed architecture, programs and data are organized in entities that are created, exist, move, adapt, and share a sea of atomic processors. If component failures render one or more atomic processors not functional, the functional integrity of the system as a whole is not affected. The architecture maximizes the exploitation of instruction and thread level parallelisms inherently available in traditional programs. The paper presents the architecture´s organization, communications protocols, and operation. Lower and upper bounds for the effective execution time of 100% sequential and 100% parallel code, respectively, are obtained using analytical methods. Further evaluation is performed using a few relevant examples. Although the proposed architecture shares traits with several known architectures, its organization, operation, and performance characteristics are unique.