Design of comparator with offset cancellation for 12-bit 1.6MS/s successive approximation ADC

This paper presents the design and simulation of 3.3V comparator with offset cancellation implemented using 0.18μm XFAB´s CMOS process technology. The comparator was designed for 12-bit 1.6MS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC). An offset cancellation technique was employed to improve comparator offset to 610μV. The comparator operates in 20MHz clock frequency while dissipates 858uW from a 3.3V supply. It occupies 56um × 118um silicon area.