Title :
A high throughput pipelined hardware architecture for tag sorting in packet fair queuing schedulers
Author :
Tu Nguyen Van;Vu Tang Thien;Son Nguyen Kim;Nam Pham Ngoc;Thanh Nguyen Huu
Author_Institution :
School of Electronics and Telecommunications, Hanoi University of Science and Technology, Vietnam
Abstract :
In a timestamp-base packet scheduler, which is an important part of Quality of Service (QoS) enabled network systems, Tag Sorting is the most critical step. This paper presents a high throughput pipelined architecture for Tag Sorting targeting FPGA technology. Our implementation results on Xilinx Virtex II pro 50 chip have shown that our design can run at a maximum clock frequency of 216 MHz and process one tag every 2 clock cycles, thus provides 108 million tags per second throughput and can support 100 Gbps line speeds.
Keywords :
"Sorting","Hardware","Quality of service","Throughput","Scheduling algorithms","Decoding","Computer architecture"
Conference_Titel :
Communications, Management and Telecommunications (ComManTel), 2015 International Conference on
DOI :
10.1109/ComManTel.2015.7394257