Delay and power consumption estimation in embedded systems using hierarchical performance modeling

Embedded systems have become very important in our life; they pervade all fields in today´s advanced technology. With the increasing importance of these systems, designers need to estimate the performance metrics such as Delay which includes processing and communication and Power consumption. This procedure is very critical and even crucial at an early stage of design and implementation. Using GPUs and parallelization schemes together shows a promising sight to enhance the delay in a system under investigation with trade-off in power consumption and code size. In this paper, we will analyze that system using Hierarchical Performance Modeling (HPM) to estimate the improvement in the delay by using GPUs and parallelization methods on different hardware architectures and software platforms. The experimental results showed an improvement in the delay each time we used more threads and maximum reduction obtained when GPU was invoked to perform all graphical tasks.