Title :
New orthogonalizing Boolean equation using in the calculation of test patterns for combinatorial circuits
Author :
Yavuz Can;Georg Fischer
Author_Institution :
Institute for Electronics Engineering, Friedrich-Alexander-University, Erlangen-Nuremberg, Germany
Abstract :
In this paper a new Boolean equation for the orthogonalization of Boolean functions respectively of Ternary-Vector-Lists of disjunctive normal form is presented. It provides the mathematical solution of orthogonalization. The new equation is based on the new method of orthogonalizing OR-ing *** which enables the building the union of two product terms respectively of two Ternary-Vectors whereby the result is orthogonal. The algorithm based on the new equation has a faster computation time in contrast to other methods. Further advantage is the smaller number of the product terms respectively of the Ternary-Vectors in the orthogonalized result which reduces the number of further calculation steps. Furthermore, the new equation can be used as a part in the calculation procedure of getting suitable test patterns for combinatorial circuits for verifying feasible logical faults.
Keywords :
"Mathematical model","TV","Boolean functions","Circuit faults","Logic gates","Manganese","Buildings"
Conference_Titel :
Electrical and Electronics Engineering (ELECO), 2015 9th International Conference on
DOI :
10.1109/ELECO.2015.7394481