DocumentCode :
3738774
Title :
A layered UVM based testbench design for SpaceWire
Author :
Ahmet ?a?r? Ba?baba;Buse Ustao?lu;?nan Erdem;Berna Ors
Author_Institution :
Istanbul Technical University, Istanbul, Turkey
fYear :
2015
Firstpage :
1164
Lastpage :
1168
Abstract :
The Universal Verification Methodology is a standard which is designed to enable creation of reusable, robust and interoperable verification IP and testbench components. In this work, we implemented layered UVM testbench for SpaceWire which is a spacecraft communication network based in part on the IEEE 1355 standard of communications. This design helps further analyzes of SpaceWire by testing different SpaceWire layers such as exchange layer and character layer. Transactions were used at all layer of protocol and user can make analysis, coverage collecting and debugging through this design. In the conclusion, all simulator results and details about Verification IP design were given.
Keywords :
"Monitoring","Instruments","Protocols","Encoding","Open systems","Clocks","Hardware design languages"
Publisher :
ieee
Conference_Titel :
Electrical and Electronics Engineering (ELECO), 2015 9th International Conference on
Type :
conf
DOI :
10.1109/ELECO.2015.7394599
Filename :
7394599
Link To Document :
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