A high performance multiply-accumulate unit with double carry-save scheme for 6-input LUT based reconfigurable systems

Redundant number systems provide carry-propagation free arithmetic, so that faster arithmetic circuits can be designed. In this work, an alternative redundant arithmetic based fused multiply-accumulate (MAC) unit is designed especially suitable for 6-input look-up-table (LUT) based FPGAs. By employing only (6, 3) counters in the partial product reduction and accumulate operations, least amount of logic depth is provided which results as high performance without any pipeline requirement in the system. The proposed MAC unit has 16×16 input with sign extended 40-bit output. The MAC unit is compared to conventional redundant carry-save and various standard MAC architectures. The proposed structure provides highest performance among the structures that have been compared.