• DocumentCode
    3738894
  • Title

    Proposal of compact analytical modeling for trigate junctionless nanowire transistors

  • Author

    Fernando ?vila-Herrera;Antonio Cerdeira;Magali Estrada;Bruna Cardoso Paz;Marcelo Antonio Pavanello

  • Author_Institution
    Secci?n de Electr?nica del Estado S?lido, Depto. Ingenier?a El?ctrica, CINVESTAV-IPN, M?xico D.F., Mexico
  • fYear
    2015
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    A compact analytical model for junctionless nanowire transistors is developed taking into account the fin height and including its capacitance. This model is based on a previous one for double-gate transistors just considering the dependence of the fin height and the short channel effects. The validation has been performed by 3D simulations for structures of 15 nm and 10 nm of height obtaining a very good agreement between modeled and simulated data.
  • Keywords
    "Solid modeling","Transistors","Three-dimensional displays","Logic gates","Analytical models","Capacitance","Semiconductor process modeling"
  • Publisher
    ieee
  • Conference_Titel
    Power, Electronics and Computing (ROPEC), 2015 IEEE International Autumn Meeting on
  • Type

    conf

  • DOI
    10.1109/ROPEC.2015.7395131
  • Filename
    7395131
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3738894