Method for sizing complex CNFET bitcells for balanced read write operation

This paper proposes a new experimental method to size CNFET circuits, especially SRAM bitcells. The paper presents read and write N-curve stability metrics and establishes the trade-off philosophy between read and write operations. The transistors in a complex 10T SRAM bitcell are sized using the algorithm and data is presented to verify the balancing criteria and balancing point. The results are replicated in a simpler 6T bitcell using the same algorithm and similar analysis is carried out. The algorithm achieves balance in the SRAM bitcell between the read and write tradeoffs whilst maintaining good individual read and write metrics.