CNTFET full-adders for energy-efficient arithmetic applications

In this paper, we present two energy-efficient full adders (FAs) which are a crucial building block of nano arithmetic logic units (nano-ALUs) with the Cell Design Methodology (CDM). Since the most suitable design configuration for CNT-based ICs is pass transistor configuration (PTL), CDM which properly benefits from PTL advantages is utilized. So the designs herewith take full advantages of simplicity, fewer transistors and better immunity against threshold voltage fluctuations of the PTL than the CCMOS configuration. CDM also resolves two problems of PTL by employing elegant mechanisms which are threshold voltage drop and loss of gain. Using the amend mechanisms and SEA sizing algorithm for CNTFETs, the proposed circuits enjoy full swing in all outputs and internal nodes, structural symmetry, reduced power-delay product (PDP) and energy-delay product (EDP), fairly balanced outputs and high driving capability. The state of the art includes both bulk CMOS and CNTFET technologies. The simulation results exhibit an average PDP and EDP improvement of 9-98% and 55-99% respectively compared with the referenced FAs. All HSPICE simulations were performed on 32nm CNTFET and CMOS process technologies.