Fast and energy efficient FinFET full adders with Cell Design Methodology (CDM)

FinFET technology has been proposed as an alternative for bulk CMOS in the ultra-low power designs has a lot of advantages like more effective channel control, lower energy consumption, high ON/OFF current ratio, etc. Some previous works have been done to compare the impact of this new technology on the circuit and evaluation of the performance advantages that can achieve. On the other side, Cell Design Methodology (CDM) as a new methodology of the design which properly benefits from PTL advantages and also resolves two problems of PTL which are threshold voltage drop and loss of gain has been proposed. In this paper, we combined CDM as the methodology of design with FinFET as technology to present three energy-efficient full adders (FAs). The proposed circuits enjoy full-swing in all outputs, structural symmetry, reduced power-delay product (PDP) and Energy delay product (EDP). The state of the art includes some known adders in FinFET technologies in comparison with the proposed adders. The Proposed FinFET adders show a delay reduction on average of 54 to 95%, PDP reduction of 33 to 76% and savings of Energy 78 to 90% respectively compared with the referred full adders. All simulations were performed on 32nm FinFET process technologies.