Power dissipation reduction using adiabatic logic techniques for CMOS inverter circuit

Power dissipation in circuits and systems is the critical factor for most of the researchers and industries. Many power dissipation techniques have been proposed but most of these techniques have some tradeoffs. Adiabatic logic technique in contrary to that of a conventional CMOS technique shows promising results. A variable supply voltage is provided instead of a constant supply required for CMOS logic. In this paper, an unconventional approach for reducing the power dissipation is reviews and implemented. Various techniques used for implementing adiabatic logic circuits are also discussed in this paper. The adiabatic CMOS and the conventional CMOS techniques are compared with respect to their power dissipation parameter. The simulation results obtained verifies that the circuits implemented using adiabatic logic approach dissipate lesser power compared to that of conventional static CMOS approach.