DocumentCode
3739099
Title
Aiding Teaching of Logic Design and Computer Organization through Dynamic Problem Generation and Automatic Checker Using COLDVL Tool
Author
Gargi Roy;Devleena Ghosh;Chittaranjan Mandal;Indraneel Mitra
Author_Institution
Dept. of Comput. Sci. &
fYear
2015
Firstpage
15
Lastpage
22
Abstract
This paper presents an approach to aid teaching of Digital Logic and Computer Organization through generation of dynamic assignment statements along with development of automatic generic checkers for those assignments using the COLDVL virtual laboratory package. Dynamically generated problem statements ensure a fairly large set of, distinct problems. The automated generic checkers allow the solutions developed by the students to be evaluated rapidly online. Here we illustrate this concept by presenting three classes of dynamic problems for three topics and their corresponding checkers. The strength of the scheme presented here is that the checker may be developed using the COLDVL tool itself and does not require the instructor to develop special skills, such as mastering formal verification techniques for this purpose. More such problem classes would need to be developed to make this scheme deployable. The results of the current effort are encouraging. Satisfactory evaluation studies of COLDVL are also presented here.
Keywords
"Testing","Computers","Organizations","Integrated circuit modeling","Logic gates","Logic design","Computational modeling"
Publisher
ieee
Conference_Titel
Technology for Education (T4E), 2015 IEEE Seventh International Conference on
Type
conf
DOI
10.1109/T4E.2015.4
Filename
7395608
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