Low Power Spatial Computing Using Null Convention Logic

We describe and analyze the design and organization of an homogeneous asynchronous bit-level array based on Null Convention Logic. A bit-element (bel) array represents a "hybrid" bit-level processor that exhibits both Spatial and tem poral computing characteristics. Bels are connected in a 2D grid, with eight-way connectivity. Programs represented as Directed Acyclic Graphs can be mapped to the array either fully statically or with a small level of element reuse (dynamic mapping). Using a 28nm FDSOI process, we present some preliminary estimation for area and power of a bel.