Chip-level programming of heterogeneous multiprocessors

Chip Heterogeneous Multiprocessors (CHMs) are increasingly emerging as a means to optimize energy and performance over a wide spectrum of application programs. However, unlike traditional processors no programming model has been developed for CHMs. This paper proposes a set of programming primitives and benchmarking strategies for CHMs. We demonstrate our proposal by showing how architects can evaluate and program chip level behavior directly and not simply rely upon traditional one size fits all schedulers. We evaluate a chip level program in terms of triggering frequency and global control state primitives for several benchmark usage patterns. Our cell phone example shows performance improvement over a baseline design by an average of 57%. System response time is improved by as much as 35%, compared to a traditional dynamic scheduler with 22% energy savings.