Testing of 3D IC with minimum power using genetic algorithm

System-on-a-chip (SOC) uses embedded cores those require a test access architecture called Test Access Mechanism (TAM) to access the cores for the purpose of testing. Optimization of TAM and test time at SOC level is an important area of research. However, the interconnect between the cores of SOC contribute to circuit delay and power consumption. Power and thermal issues are major concern, specially during testing the design under test (DUT) consumes significantly more power in test mode than in normal operation. To reduce the interconnect 3D IC is a solution where multiple device layers are stacked together. The problem of high test power consumption can be solved by the use of power aware test planning in 3D IC. In this paper, we have addressed the problem and proposed genetic algorithm based approach for power aware test planning. Given a TAM width available to test a SOC, our algorithm partitions this width into different groups and places the cores of these groups in different layers in core based SOCs based on 3D IC technology with the goal to optimize the total test time under certain power limit. In addition to this our technique also takes into account minimum power during testing, where the goal is to optimize the total test time with minimum power. The experimental results establish the effectiveness of our algorithm.