SR-TPG: A low transition test pattern generator for test-per-clock and test-per-scan BIST

This paper presents the use of switch-tail ring counter as low transition test pattern generator (TPG) to reduce power consumption in test-per-clock and test-per-scan built-in self-test (BIST) applications. The proposed TPG is implemented by dividing the register in the test mode into many switch-tail ring counters. These counters are fed with a seed in such a way to produce a single transition between consecutive test patterns. Also each of these ring counters are triggered with a clock and control signal such that not all the counters are triggered with each clock in order to reduce the switching activity in the inputs of the circuit-under-test (CUT). The proposed technique can be used for test-per-clock and test-per-scan BIST. Various properties of the proposed technique and the methodology of the design are presented in this paper. Experimental results for ISCAS´85 (test-per-clock) and for the ISCAS´89 (test-per-scan) benchmark circuits show that the proposed design can reduce the switching activity with an average of 84% and 72%, respectively.