A CMOS analog front end for ADCs

A CMOS analog front end for ADCs is introduced, which can sample and hold the incoming analog signal for the following ADC. As a result, the ADC can deal with a signal which is unchanged at the working period of the ADC. The analog front is a full differential architecture including two completely symmetrical signal paths, which receive the normal and inverted phase parts of a full differential signal, respectively. The outputs of the two signal paths are inputted into the normal and inverted phase input terminals of a full differential amplifier. A protection is added to the circuit to speed up the sampling switch. A resistor is added to filter out the high frequency spur caused by the switching action of circuit. As a result, the proposed circuit has higher sampling rate and performances than other related sample and hold circuit. Simulation shows that the analog front consumes only 80mW power and has a SNR of 67dB as well as a SFDR of 70dB at a sampling rate of 2.4GSPS.