DocumentCode :
3741357
Title :
The A to Z of building a testbed for Power Analysis attacks
Author :
Hasindu Gamaarachchi;Harsha Ganegoda;Roshan Ragel
Author_Institution :
Department of Computer Engineering, University of Peradeniya, Sri Lanka
fYear :
2015
Firstpage :
501
Lastpage :
506
Abstract :
Correlation Power Analysis (CPA) based Side Channel Attack (SCA) is a popular modern cryptanalysis typically used by adversaries in embedded devices to break their secret keys. CPA uses the correlation between the power consumption of the cryptosystem and the computation performed to derive the secret key. Proposing countermeasures against such attacks require a testbed for implementation and verification. Although, a large number of such attacks and countermeasures are proposed in the literature, building of testbeds are still not presented properly. Therefore, researchers starting to work on CPA have to spend an enormous amount of time for building and debugging such testbeds. Also, a few testbeds presented in the literature have their limitations. In this paper, we present an A to Z guide for preparing a CPA testbed that also addresses the shortcomings of the existing testbeds in the literature.
Keywords :
"Cryptography","Universal Serial Bus","Oscillators","Resistors"
Publisher :
ieee
Conference_Titel :
Industrial and Information Systems (ICIIS), 2015 IEEE 10th International Conference on
Print_ISBN :
978-1-5090-1741-6
Type :
conf
DOI :
10.1109/ICIINFS.2015.7399063
Filename :
7399063
Link To Document :
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