Simplified pseudo-dynamic receive beamforming for FPGA implementation

An algorithm to reduce computational time for pseudo-dynamic receive beamforming using FPGA is presented. This includes a method to store and retrieve the predetermined delays and other parameters. In addition, we present a simplified implementation method to compute the scanline one sample at a time. The addresses of the echo signal data from different piezoelectric elements are parallel calculated using the delays. Subsequently, the data are loaded and summed, resulting in one sample on the scanline. This method is easy to be modified for delay error compensation and for different window lengths. This algorithm is implemented on an FPGA (Virtex-4, Xilinx, inc., San Jose, CA) and providing fast computational time of 0.998 ms per scanline for 8192 samples at 40-MHz sampling with comparable image qualities to dynamic receive beamforming.