An architecture of fast data recovery in UHF RFID reader

Architecture of fast data recovery was introduced into the design of the digital receiver in UHF RFID Reader. The data should be recovered in a short time for the next step of decoding. Rich synchronizing information in Miller coding was used to improve the quality of decoding in a poor situation. The architecture of fast data recovery consisted of edge detector, period measure, cnt_syn and data recovery modules. The proposed architecture of data recovery had been evaluated in the FPGA platform. The data could be fast recovered from different frequency of a high deviation with less hardware cost.