Hardware implementation of linear back-projection algorithm for capacitance tomography

This paper presents method to implement Linear Back Projection (LBP) algorithm in Field Programmable Gate Arrays (FPGA). Top-down approach has been adopted for the design of the hardware of LBP algorithm. The FPGA used is Xilinx Spartan 3A and the language used to design the hardware is VHSIC Hardware Description Language (VHDL). The final design is able to reconstruct a 32×32 pixel image from 8-electrode Electrical Capacitance Tomography (ECT) with speed of 23809 slice images per second and the image is shown on LCD. It could be further extended to form quasi 3D image with 32 slices at rate 744 frame-per-second.