• DocumentCode
    3742560
  • Title

    A low-voltage PLL with a current mismatch compensated charge pump

  • Author

    Sung-Geun Kim;Jinsoo Rhim;Dae-Hyun Kwon;Min-Hyeong Kim;Woo-Young Choi

  • Author_Institution
    Department of Electrical and Electronic Engineering, Yonsei University, Seodaemun-gu, Seoul 120-749, Korea
  • fYear
    2015
  • Firstpage
    15
  • Lastpage
    16
  • Abstract
    A low-voltage phase-locked loop (PLL) circuit having a charge pump (CP) with a novel negative feedback replica bias scheme for current mismatch compensation is demonstrated. A prototype 400-MHz PLL circuit operating at 0.65-V is fabricated with 180-nm standard CMOS process. Measurement results show that current mismatch compensation is successfully achieved. Our PLL consumes only 140-μW.
  • Keywords
    "Phase locked loops","Charge pumps","CMOS integrated circuits","Current measurement","Logic gates","Negative feedback","CMOS technology"
  • Publisher
    ieee
  • Conference_Titel
    SoC Design Conference (ISOCC), 2015 International
  • Type

    conf

  • DOI
    10.1109/ISOCC.2015.7401629
  • Filename
    7401629
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3742560