Design of a 40GHz PLL frequency synthesizer with wide locking range ILFD in 65nm CMOS

A 40GHz PLL synthesizer is designed in 65nm CMOS for a 60GHz sliding-IF RF transceiver for IEEE 802.11ad applications. For wide locking range, ILFD employs a 5-bit switched capacitor array and a inductive peaking at the injection FET. The ILFD´s locking range is wider than the VCO´s tuning range, which ensures the PLL can safely lock across the VCO´s full tuning range. Also, a tuned buffer with a boosted Q load is employed to minimize unwanted interaction between the VCO and ILFD´s operating frequencies, which also helps widen the PLL´s locking range. The PLL synthesizer is designed in 65nm CMOS and its die area is 1.0×1.1mm2.