A 12b 60MS/s 0.11?m Flash-SAR ADC using a mismatch-free shared sampling network

This work proposes a 12b 60MS/s 0.11μm CMOS Flash-SAR ADC for wireless communication systems. The proposed Flash-SAR ADC is implemented with a 4b flash ADC and a 9b SAR ADC for high speed operation with low power consumption. Furthermore, the shared single sampling-network minimizes a sampling-time mismatch between the flash ADC and the SAR ADC, which is commonly observed in a Flash-SAR ADC without a T/H circuit. The prototype ADC occupies an active die area of 0.31mm² and consumes 3.2mW at a 1.2V supply voltage.