Design of a 10 bit 50MS/s SAR ADC in 14nm SOI FinFET CMOS

This paper presents a 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) with 60.9 dB SNDR at 50MS/s while with 41.3uW power consumption. Several techniques were used to decrease the power consumption. First, Segmented architecture was used to decrease the total number of capacitance. Aligned switching with skip (ASS) method was used during copy MSB bits from coarse to fine, which saves 58% switching power. Second, the normal SAR switching is based on VCM-based switching algorithm; it saves 85.72% power compared with traditional SAR. Third, dual supply mode with analog at 0.8V and digital at 0.4V was used to decrease the digital logic power consumption, simulation results show that it saves 23% total power consumption at dual supply mode. Differential architecture was used to minimize the commode non-idealities. The proposed ADC achieved a peak figure of merit (FoM) of 0.93 fJ/Conv with simulation results in 14nm SOI FinFET technology.