A design guideline for volatile STT-RAM with ECC and scrubbing

STT-RAM is considered as a promising alternative to SRAM due to its low static power (non-volatility) and high density. However, write operation of STT-RAM is inefficient in terms of energy and speed compared to SRAM and thus STT-RAM with low retention time (volatile STT-RAM) has been proposed at the cost of scrubbing and error correcting code (ECC). The more frequent scrubbing and stronger ECC are used, the shorter retention time is allowed. Based on extensive experiment and analytic STT-RAM model, this paper provides a guideline for designing a volatile STT-RAM with ECC and scrubbing.