FPGA implementation of JADE ICA algorithm

Blind Source Separation (BSS) has gained recognition in its application to many different fields of research such as medical, military, and industry fields. Of the many challenges that must be overcome to apply BSS to a real system, implementation restrictions are the most challenging. Software implementations require a significant amount of overhead to make them applicable to real-time systems, and have a lower maximum speed of operation than hardware implementations. When speed is desired, the algorithm should be implemented on specialized hardware such as a Field Programmable Gate Array (FPGA) which allows the user to take advantage of parallel computational abilities. In this paper, a hardware implementation of the Joint Approximation and Diagonalization of Eigenmatrices (JADE) algorithm is compared with software implementations. The algorithm is implemented in VHDL on an Artix-7 XC7A100T FPGA. The effective speed of source separation, cost of equipment, and ease of use can all be improved via a hardware implementation.