Title :
A review of on-chip timing error detection/correction methods for logic pipeline
Author_Institution :
Dept. of Creative IT Engineering, Pohang University of Science and Technology (POSTECH) Pohang, Korea
Abstract :
We review the technical trend for on-chip timing error detection/correction schemes to reduce the excessive timing margin in digital circuit design. Starting with the RAZOR [1] scheme which is one of the most popular on-chip timing error detection/correction schemes, we summarize the related technical challenges and the state-of-the-art solutions to overcome them.
Keywords :
"Latches","Timing","Error correction","Pipelines","Flip-flops","Clocks","Pipeline processing"
Conference_Titel :
SoC Design Conference (ISOCC), 2015 International
DOI :
10.1109/ISOCC.2015.7401660
