Area performance tradeoffs in NCL multipliers using two-dimensional pipelining

The natural pipelining behavior of Null Convention Logic (NCL) can often result in high speed data paths with fewer gate delays. However, the spanning completion detection and shared completeness path of the NCL handshaking signal may need very large completion detection gates that exhibit excessive fan-in, long propagation delays and high capacitance. Fine grained Two-Dimensional (2D) Pipelining for NCL circuits has been suggested as a potential solution. In this paper, we show a high throughput multiplier design based on 2D pipelining with NCL and compare it to equivalent non-pipelined and 1D pipelined case. We show an overall performance improvement of 260% in exchange for a similar area penalty.