A scan segment skip technique for low power test

Excessive power consumption during testing has been one of the most important issues from the exponential advance in semiconductor manufacturing technology. In this paper, a scan segment skip technique is proposed to reduce power consumption by skipping segments that don´t need scan in/out processes. Also, a new pattern merge algorithm is proposed for maximizing power reduction ratio. Experimental results show that the proposed technique efficiently reduces test power consumption with the minimal impact on area overhead.