Static fault analysis for resilient System-on-Chip design

As a process technology is scaling, a reliability problem that may cause a failure in the functionality of the digital circuit becomes an important issue in System-on-Chip (SoC) design. This importance leads to the studies on fault diagnosis and tolerance. In this paper, we propose a static and analytical technique for fault diagnosis focused on the digital circuit. Gate level fault analysis is completed in accordance with characteristic of logic gates and error propagation, predicting a susceptible part of hardware. Gate level fault diagnosis can be realized by parsing a gate level netlist without simulation, reducing the verification time. Moreover, our proposal provides an abstraction between the user and the target system for fault diagnosis and helps users choose appropriate fault-tolerant technology for the system. The error propagation analysis with an example combinational logic shows the feasibility of our proposal for resilient SoC design.