A high-resolution on-chip propagation delay measurement scheme

We propose a high-resolution on-chip propagation delay measurement scheme. The scheme uses a pair of coherent equivalent-time sampling 1-bit digitizers. The scheme does not require complex circuits to be added on-chip, has reasonable test-time, and is not liable to the "bunching" effect. A test-chip was fabricated to characterize the propagation delay of a 65nm CMOS programmable I/O buffer using the proposed scheme. The measurements have 10ps resolution, tally with simulations, and are precise with o of lower than 1% the respective measured values. Measurements with higher resolution are possible.