Hardware optimizations of hard-decision ECC decoders for MLC NAND flash memories

This paper summarizes various optimization schemes of BCH-based error-correction code (ECC) decoders for commercialized NAND flash memories. To improve the energy efficiency by relaxing the decoding energy consumption or by increasing the decoding throughput, the decoder architectures are carefully analyzed to share the internal processing units. The enhanced folding technique can be applied to reduce the hardware complexity further while constructing the regular pipelined processing. In addition, the pre-processing method can be used for reducing the number of on-chip SRAM memory accesses in decoding of BCH-based product codes, saving the decoding energy significantly.